2012-10-06 15:21:23 +00:00
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/*
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* Copyright 2008 Veselin Georgiev,
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* anrieffNOSPAM @ mgail_DOT.com (convert to gmail)
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __CPUID_H__
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#define __CPUID_H__
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#ifdef __x86_64__
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#define VENDOR_STR_MAX 16
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#define BRAND_STR_MAX 64
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#define CPU_FLAGS_MAX 128
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#define MAX_CPUID_LEVEL 32
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#define MAX_EXT_CPUID_LEVEL 32
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#define MAX_INTELFN4_LEVEL 4
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2013-01-26 10:09:10 +00:00
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typedef enum {
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PROC_BIGENDIAN_GENERIC = 1,
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PROC_LITENDIAN_GENERIC,
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PROC_X64_INTEL,
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PROC_X64_AMD
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} proc_type_t;
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typedef struct {
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int sse_level;
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int sse_sub_level;
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int avx_level;
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int xop_avail;
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proc_type_t proc_type;
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} processor_info_t;
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2012-10-06 15:21:23 +00:00
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/**
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* This contains only the most basic CPU data, required to do identification
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* and feature recognition. Every processor should be identifiable using this
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* data only.
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*/
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struct cpu_raw_data_t {
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/** contains results of CPUID for eax = 0, 1, ...*/
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uint32_t basic_cpuid[MAX_CPUID_LEVEL][4];
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/** contains results of CPUID for eax = 0x80000000, 0x80000001, ...*/
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uint32_t ext_cpuid[MAX_EXT_CPUID_LEVEL][4];
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/** when the CPU is intel and it supports deterministic cache
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information: this contains the results of CPUID for eax = 4
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and ecx = 0, 1, ... */
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uint32_t intel_fn4[MAX_INTELFN4_LEVEL][4];
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char vendor_str[VENDOR_STR_MAX];
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};
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void exec_cpuid(uint32_t *regs);
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void cpuid_get_raw_data(struct cpu_raw_data_t* data);
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2012-12-27 17:36:48 +00:00
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void cpuid_basic_identify(processor_info_t *pc);
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2012-10-06 15:21:23 +00:00
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#endif /* __x86_64__ */
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#endif /* __CPUID_H__ */
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