26bb137257
Multi instruction set XXhash build with runtime selection. Extend CPUID code to detect more instruction sets. Add options for BLAKE2 hash. Move GCC builtins into utils header. Bump file format version number due to extended digest flags. Add descriptions to digest list.
497 lines
16 KiB
C
497 lines
16 KiB
C
/*
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xxHash - Fast Hash algorithm
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Copyright (C) 2012, Yann Collet.
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BSD 2-Clause License (http://www.opensource.org/licenses/bsd-license.php)
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are
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met:
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* Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above
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copyright notice, this list of conditions and the following disclaimer
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in the documentation and/or other materials provided with the
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distribution.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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You can contact the author at :
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- xxHash source repository : http://code.google.com/p/xxhash/
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*/
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//**************************************
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// Tuning parameters
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//**************************************
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// FORCE_NATIVE_FORMAT :
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// By default, xxHash library provides endian-independant Hash values.
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// Results are therefore identical for big-endian and little-endian CPU.
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// This comes at a performance cost for big-endian CPU, since some swapping is required to emulate little-endian format.
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// Should endian-independance be of no importance to your application, you may uncomment the #define below
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// It will improve speed for Big-endian CPU.
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// This option has no impact on Little_Endian CPU.
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//#define FORCE_NATIVE_FORMAT 1
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//**************************************
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// Includes
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//**************************************
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#include <stdlib.h> // for malloc(), free()
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#include <string.h> // for memcpy()
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#include "xxhash.h"
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//**************************************
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// CPU Feature Detection
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//**************************************
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// Little Endian or Big Endian ?
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// You can overwrite the #define below if you know your architecture endianess
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#if defined(FORCE_NATIVE_FORMAT) && (FORCE_NATIVE_FORMAT==1)
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// Force native format. The result will be endian dependant.
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# define XXH_BIG_ENDIAN 0
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#elif defined (__GLIBC__)
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# include <endian.h>
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# if (__BYTE_ORDER == __BIG_ENDIAN)
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# define XXH_BIG_ENDIAN 1
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# endif
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#elif (defined(__BIG_ENDIAN__) || defined(__BIG_ENDIAN) || defined(_BIG_ENDIAN)) && !(defined(__LITTLE_ENDIAN__) || defined(__LITTLE_ENDIAN) || defined(_LITTLE_ENDIAN))
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# define XXH_BIG_ENDIAN 1
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#elif defined(__sparc) || defined(__sparc__) \
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|| defined(__ppc__) || defined(_POWER) || defined(__powerpc__) || defined(_ARCH_PPC) || defined(__PPC__) || defined(__PPC) || defined(PPC) || defined(__powerpc__) || defined(__powerpc) || defined(powerpc) \
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|| defined(__hpux) || defined(__hppa) \
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|| defined(_MIPSEB) || defined(__s390__)
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# define XXH_BIG_ENDIAN 1
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#endif
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#if !defined(XXH_BIG_ENDIAN)
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// Little Endian assumed. PDP Endian and other very rare endian format are unsupported.
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# define XXH_BIG_ENDIAN 0
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#endif
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//**************************************
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// Compiler-specific Options & Functions
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//**************************************
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#define GCC_VERSION (__GNUC__ * 100 + __GNUC_MINOR__)
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// Note : under GCC, it may sometimes be faster to enable the (2nd) macro definition, instead of using win32 intrinsic
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#if defined(_WIN32)
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# define XXH_rotl32(x,r) _rotl(x,r)
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#else
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# define XXH_rotl32(x,r) ((x << r) | (x >> (32 - r)))
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#endif
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#if defined(_MSC_VER) // Visual Studio
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# define XXH_swap32 _byteswap_ulong
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#elif GCC_VERSION >= 403
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# define XXH_swap32 __builtin_bswap32
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#else
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static inline unsigned int XXH_swap32 (unsigned int x) {
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return ((x << 24) & 0xff000000 ) |
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((x << 8) & 0x00ff0000 ) |
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((x >> 8) & 0x0000ff00 ) |
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((x >> 24) & 0x000000ff );
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}
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#endif
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#if defined(__USE_SSE_INTRIN__) && defined(__SSE4_1__)
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#include <smmintrin.h>
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static inline __m128i _x_mm_rotl_epi32(const __m128i a, int bits)
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{
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__m128i tmp1 = _mm_slli_epi32(a, bits);
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__m128i tmp2 = _mm_srli_epi32(a, 32 - bits);
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return (_mm_or_si128(tmp1, tmp2));
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}
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#endif
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//**************************************
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// Constants
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//**************************************
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#define PRIME32_1 2654435761U
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#define PRIME32_2 2246822519U
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#define PRIME32_3 3266489917U
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#define PRIME32_4 668265263U
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#define PRIME32_5 374761393U
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//**************************************
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// Macros
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//**************************************
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#define XXH_LE32(p) (XXH_BIG_ENDIAN ? XXH_swap32(*(unsigned int*)(p)) : *(unsigned int*)(p))
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//****************************
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// Simple Hash Functions
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//****************************
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unsigned int CPUCAP_NM(XXH32)(const void* input, int len, unsigned int seed)
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{
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#if 0
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// Simple version, good for code maintenance, but unfortunately slow for small inputs
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void* state = XXH32_init(seed);
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XXH32_feed(state, input, len);
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return XXH32_result(state);
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#else
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const unsigned char* p = (const unsigned char*)input;
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const unsigned char* p1 = p;
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const unsigned char* const bEnd = p + len;
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unsigned int h32;
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if (len>=32)
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{
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const unsigned char* const limit = bEnd - 32;
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unsigned int v1 = seed + PRIME32_1 + PRIME32_2;
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unsigned int v2 = seed + PRIME32_2;
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unsigned int v3 = seed + 0;
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unsigned int v4 = seed - PRIME32_1;
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#if defined(__USE_SSE_INTRIN__) && defined(__SSE4_1__)
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unsigned int vx[4], vx1[4];
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__m128i accum = _mm_set_epi32(v4, v3, v2, v1);
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__m128i accum1 = _mm_set_epi32(v4, v3, v2, v1);
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__m128i prime1 = _mm_set1_epi32(PRIME32_1);
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__m128i prime2 = _mm_set1_epi32(PRIME32_2);
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/*
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* 4-way SIMD calculations with 4 ints in two blocks for 2 accumulators will
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* interleave to some extent on a hyperthreaded processor providing 10% - 14%
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* speedup over original xxhash depending on processor. We could have used
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* aligned loads but we actually want the unaligned penalty. It helps to
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* interleave better for a slight benefit over aligned loads here!
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*/
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do {
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__m128i mem = _mm_loadu_si128((__m128i *)p);
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p += 16;
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mem = _mm_mullo_epi32(mem, prime2);
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accum = _mm_add_epi32(accum, mem);
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accum = _x_mm_rotl_epi32(accum, 13);
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accum = _mm_mullo_epi32(accum, prime1);
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mem = _mm_loadu_si128((__m128i *)p);
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p += 16;
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mem = _mm_mullo_epi32(mem, prime2);
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accum1 = _mm_add_epi32(accum1, mem);
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accum1 = _x_mm_rotl_epi32(accum1, 13);
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accum1 = _mm_mullo_epi32(accum1, prime1);
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} while (p<=limit);
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_mm_storeu_si128((__m128i *)vx, accum);
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_mm_storeu_si128((__m128i *)vx1, accum1);
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/*
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* Combine the two accumulators into a single hash value.
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*/
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v1 = vx[0];
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v2 = vx[1];
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v3 = vx[2];
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v4 = vx[3];
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v1 += vx1[0] * PRIME32_2; v1 = XXH_rotl32(v1, 13); v1 *= PRIME32_1;
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v2 += vx1[1] * PRIME32_2; v2 = XXH_rotl32(v2, 13); v2 *= PRIME32_1;
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v3 += vx1[2] * PRIME32_2; v3 = XXH_rotl32(v3, 13); v3 *= PRIME32_1;
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v4 += vx1[3] * PRIME32_2; v4 = XXH_rotl32(v4, 13); v4 *= PRIME32_1;
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h32 = XXH_rotl32(v1, 1) + XXH_rotl32(v2, 7) + XXH_rotl32(v3, 12) + XXH_rotl32(v4, 18);
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#else
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unsigned int vx1 = seed + PRIME32_1 + PRIME32_2;
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unsigned int vx2 = seed + PRIME32_2;
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unsigned int vx3 = seed + 0;
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unsigned int vx4 = seed - PRIME32_1;
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do
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{
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v1 += XXH_LE32(p) * PRIME32_2; v1 = XXH_rotl32(v1, 13); v1 *= PRIME32_1; p+=4;
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v2 += XXH_LE32(p) * PRIME32_2; v2 = XXH_rotl32(v2, 13); v2 *= PRIME32_1; p+=4;
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v3 += XXH_LE32(p) * PRIME32_2; v3 = XXH_rotl32(v3, 13); v3 *= PRIME32_1; p+=4;
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v4 += XXH_LE32(p) * PRIME32_2; v4 = XXH_rotl32(v4, 13); v4 *= PRIME32_1; p+=4;
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vx1 += XXH_LE32(p) * PRIME32_2; vx1 = XXH_rotl32(vx1, 13); vx1 *= PRIME32_1; p+=4;
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vx2 += XXH_LE32(p) * PRIME32_2; vx2 = XXH_rotl32(vx2, 13); vx2 *= PRIME32_1; p+=4;
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vx3 += XXH_LE32(p) * PRIME32_2; vx3 = XXH_rotl32(vx3, 13); vx3 *= PRIME32_1; p+=4;
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vx4 += XXH_LE32(p) * PRIME32_2; vx4 = XXH_rotl32(vx4, 13); vx4 *= PRIME32_1; p+=4;
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} while (p<=limit) ;
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v1 += vx1 * PRIME32_2; v1 = XXH_rotl32(v1, 13); v1 *= PRIME32_1;
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v2 += vx2 * PRIME32_2; v2 = XXH_rotl32(v2, 13); v2 *= PRIME32_1;
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v3 += vx3 * PRIME32_2; v3 = XXH_rotl32(v3, 13); v3 *= PRIME32_1;
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v4 += vx4 * PRIME32_2; v4 = XXH_rotl32(v4, 13); v4 *= PRIME32_1;
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h32 = XXH_rotl32(v1, 1) + XXH_rotl32(v2, 7) + XXH_rotl32(v3, 12) + XXH_rotl32(v4, 18);
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#endif
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len = p - p1;
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}
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else
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{
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h32 = seed + PRIME32_5;
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}
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h32 += (unsigned int) len;
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while (p<=bEnd-4)
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{
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h32 += XXH_LE32(p) * PRIME32_3;
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h32 = XXH_rotl32(h32, 17) * PRIME32_4 ;
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p+=4;
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}
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while (p<bEnd)
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{
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h32 += (*p) * PRIME32_5;
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h32 = XXH_rotl32(h32, 11) * PRIME32_1 ;
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p++;
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}
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h32 ^= h32 >> 15;
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h32 *= PRIME32_2;
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h32 ^= h32 >> 13;
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h32 *= PRIME32_3;
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h32 ^= h32 >> 16;
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return h32;
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#endif
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}
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//****************************
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// Advanced Hash Functions
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//****************************
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struct XXH_state32_t
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{
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unsigned int seed;
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unsigned int v1, vx1;
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unsigned int v2, vx2;
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unsigned int v3, vx3;
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unsigned int v4, vx4;
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unsigned long long total_len;
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char memory[32];
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int memsize;
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};
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void* CPUCAP_NM(XXH32_init) (unsigned int seed)
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{
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struct XXH_state32_t * state = (struct XXH_state32_t *) malloc ( sizeof(struct XXH_state32_t));
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state->seed = seed;
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state->v1 = seed + PRIME32_1 + PRIME32_2;
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state->v2 = seed + PRIME32_2;
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state->v3 = seed + 0;
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state->v4 = seed - PRIME32_1;
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state->vx1 = seed + PRIME32_1 + PRIME32_2;
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state->vx2 = seed + PRIME32_2;
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state->vx3 = seed + 0;
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state->vx4 = seed - PRIME32_1;
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state->total_len = 0;
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state->memsize = 0;
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return (void*)state;
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}
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int CPUCAP_NM(XXH32_feed) (void* state_in, const void* input, int len)
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{
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struct XXH_state32_t * state = state_in;
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const unsigned char* p = (const unsigned char*)input;
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const unsigned char* const bEnd = p + len;
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state->total_len += len;
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if (state->memsize + len < 32) // fill in tmp buffer
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{
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memcpy(state->memory + state->memsize, input, len);
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state->memsize += len;
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return 0;
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}
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if (state->memsize) // some data left from previous feed
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{
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memcpy(state->memory + state->memsize, input, 32-state->memsize);
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{
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const unsigned int* p32 = (const unsigned int*)state->memory;
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state->v1 += XXH_LE32(p32) * PRIME32_2; state->v1 = XXH_rotl32(state->v1, 13); state->v1 *= PRIME32_1;
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p32++;
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state->v2 += XXH_LE32(p32) * PRIME32_2; state->v2 = XXH_rotl32(state->v2, 13); state->v2 *= PRIME32_1;
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p32++;
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state->v3 += XXH_LE32(p32) * PRIME32_2; state->v3 = XXH_rotl32(state->v3, 13); state->v3 *= PRIME32_1;
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p32++;
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state->v4 += XXH_LE32(p32) * PRIME32_2; state->v4 = XXH_rotl32(state->v4, 13); state->v4 *= PRIME32_1;
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p32++;
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state->vx1 += XXH_LE32(p32) * PRIME32_2; state->vx1 = XXH_rotl32(state->vx1, 13); state->vx1 *= PRIME32_1;
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p32++;
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state->vx2 += XXH_LE32(p32) * PRIME32_2; state->vx2 = XXH_rotl32(state->vx2, 13); state->vx2 *= PRIME32_1;
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p32++;
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state->vx3 += XXH_LE32(p32) * PRIME32_2; state->vx3 = XXH_rotl32(state->vx3, 13); state->vx3 *= PRIME32_1;
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p32++;
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state->vx4 += XXH_LE32(p32) * PRIME32_2; state->vx4 = XXH_rotl32(state->vx4, 13); state->vx4 *= PRIME32_1;
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p32++;
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}
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p += 32-state->memsize;
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len -= 32-state->memsize;
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state->memsize = 0;
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}
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if (len>=32)
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{
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const unsigned char* const limit = bEnd - 32;
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#if defined(__USE_SSE_INTRIN__) && defined(__SSE4_1__)
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unsigned int vx[4], vx1[4];
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__m128i accum = _mm_set_epi32(state->v4, state->v3, state->v2, state->v1);
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__m128i accum1 = _mm_set_epi32(state->v4, state->v3, state->v2, state->v1);
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__m128i prime1 = _mm_set1_epi32(PRIME32_1);
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__m128i prime2 = _mm_set1_epi32(PRIME32_2);
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/*
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* 4-way SIMD calculations with 4 ints in two blocks for 2 accumulators will
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* interleave to some extent on a hyperthreaded processor providing 10% - 14%
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* speedup over original xxhash depending on processor. We could have used
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* aligned loads but we actually want the unaligned penalty. It helps to
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* interleave better for a slight benefit over aligned loads here!
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*/
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do {
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__m128i mem = _mm_loadu_si128((__m128i *)p);
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p += 16;
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mem = _mm_mullo_epi32(mem, prime2);
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accum = _mm_add_epi32(accum, mem);
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accum = _x_mm_rotl_epi32(accum, 13);
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accum = _mm_mullo_epi32(accum, prime1);
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mem = _mm_loadu_si128((__m128i *)p);
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p += 16;
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mem = _mm_mullo_epi32(mem, prime2);
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accum1 = _mm_add_epi32(accum1, mem);
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accum1 = _x_mm_rotl_epi32(accum1, 13);
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accum1 = _mm_mullo_epi32(accum1, prime1);
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} while (p<=limit);
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_mm_storeu_si128((__m128i *)vx, accum);
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_mm_storeu_si128((__m128i *)vx1, accum1);
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/*
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* Combine the two accumulators into a single hash value.
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*/
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state->v1 = vx[0];
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state->v2 = vx[1];
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state->v3 = vx[2];
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state->v4 = vx[3];
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state->vx1 = vx1[0];
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state->vx2 = vx1[1];
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state->vx3 = vx1[2];
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state->vx4 = vx1[3];
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#else
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unsigned int v1 = state->v1;
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unsigned int v2 = state->v2;
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unsigned int v3 = state->v3;
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unsigned int v4 = state->v4;
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unsigned int vx1 = state->vx1;
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unsigned int vx2 = state->vx2;
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unsigned int vx3 = state->vx3;
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unsigned int vx4 = state->vx4;
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do
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{
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v1 += XXH_LE32(p) * PRIME32_2; v1 = XXH_rotl32(v1, 13); v1 *= PRIME32_1; p+=4;
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v2 += XXH_LE32(p) * PRIME32_2; v2 = XXH_rotl32(v2, 13); v2 *= PRIME32_1; p+=4;
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v3 += XXH_LE32(p) * PRIME32_2; v3 = XXH_rotl32(v3, 13); v3 *= PRIME32_1; p+=4;
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v4 += XXH_LE32(p) * PRIME32_2; v4 = XXH_rotl32(v4, 13); v4 *= PRIME32_1; p+=4;
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vx1 += XXH_LE32(p) * PRIME32_2; vx1 = XXH_rotl32(vx1, 13); vx1 *= PRIME32_1; p+=4;
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vx2 += XXH_LE32(p) * PRIME32_2; vx2 = XXH_rotl32(vx2, 13); vx2 *= PRIME32_1; p+=4;
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vx3 += XXH_LE32(p) * PRIME32_2; vx3 = XXH_rotl32(vx3, 13); vx3 *= PRIME32_1; p+=4;
|
|
vx4 += XXH_LE32(p) * PRIME32_2; vx4 = XXH_rotl32(vx4, 13); vx4 *= PRIME32_1; p+=4;
|
|
} while (p<=limit) ;
|
|
|
|
state->v1 = v1;
|
|
state->v2 = v2;
|
|
state->v3 = v3;
|
|
state->v4 = v4;
|
|
state->vx1 = vx1;
|
|
state->vx2 = vx2;
|
|
state->vx3 = vx3;
|
|
state->vx4 = vx4;
|
|
#endif
|
|
}
|
|
|
|
if (p < bEnd)
|
|
{
|
|
memcpy(state->memory, p, bEnd-p);
|
|
state->memsize = bEnd-p;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
unsigned int CPUCAP_NM(XXH32_getIntermediateResult) (void* state_in)
|
|
{
|
|
struct XXH_state32_t * state = state_in;
|
|
unsigned char * p = (unsigned char*)state->memory;
|
|
unsigned char* bEnd = (unsigned char*)state->memory + state->memsize;
|
|
unsigned int h32;
|
|
|
|
|
|
if (state->total_len >= 32)
|
|
{
|
|
unsigned int v1 = state->v1;
|
|
unsigned int v2 = state->v2;
|
|
unsigned int v3 = state->v3;
|
|
unsigned int v4 = state->v4;
|
|
|
|
v1 += state->vx1 * PRIME32_2; v1 = XXH_rotl32(v1, 13); v1 *= PRIME32_1;
|
|
v2 += state->vx2 * PRIME32_2; v2 = XXH_rotl32(v2, 13); v2 *= PRIME32_1;
|
|
v3 += state->vx3 * PRIME32_2; v3 = XXH_rotl32(v3, 13); v3 *= PRIME32_1;
|
|
v4 += state->vx4 * PRIME32_2; v4 = XXH_rotl32(v4, 13); v4 *= PRIME32_1;
|
|
h32 = XXH_rotl32(v1, 1) + XXH_rotl32(v2, 7) + XXH_rotl32(v3, 12) + XXH_rotl32(v4, 18);
|
|
}
|
|
else
|
|
{
|
|
h32 = state->seed + PRIME32_5;
|
|
}
|
|
|
|
h32 += (unsigned int) state->total_len;
|
|
|
|
while (p<=bEnd-4)
|
|
{
|
|
h32 += XXH_LE32(p) * PRIME32_3;
|
|
h32 = XXH_rotl32(h32, 17) * PRIME32_4 ;
|
|
p+=4;
|
|
}
|
|
|
|
while (p<bEnd)
|
|
{
|
|
h32 += (*p) * PRIME32_5;
|
|
h32 = XXH_rotl32(h32, 11) * PRIME32_1 ;
|
|
p++;
|
|
}
|
|
|
|
h32 ^= h32 >> 15;
|
|
h32 *= PRIME32_2;
|
|
h32 ^= h32 >> 13;
|
|
h32 *= PRIME32_3;
|
|
h32 ^= h32 >> 16;
|
|
|
|
return h32;
|
|
}
|
|
|
|
|
|
unsigned int CPUCAP_NM(XXH32_result) (void* state_in)
|
|
{
|
|
unsigned int h32 = CPUCAP_NM(XXH32_getIntermediateResult)(state_in);
|
|
|
|
free(state_in);
|
|
|
|
return h32;
|
|
}
|