577 lines
16 KiB
NASM
577 lines
16 KiB
NASM
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; Copyright 2012 Intel Corporation All Rights Reserved.
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;
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; The source code contained or described herein and all documents
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; related to the source code ("Material") are owned by Intel Corporation
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; or its suppliers or licensors. Title to the Material remains with
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; Intel Corporation or its suppliers and licensors. The Material may
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; contain trade secrets and proprietary and confidential information of
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; Intel Corporation and its suppliers and licensors, and is protected by
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; worldwide copyright and trade secret laws and treaty provisions. No
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; part of the Material may be used, copied, reproduced, modified,
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; published, uploaded, posted, transmitted, distributed, or disclosed in
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; any way without Intel's prior express written permission.
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;
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; No license under any patent, copyright, trade secret or other
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; intellectual property right is granted to or conferred upon you by
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; disclosure or delivery of the Materials, either expressly, by
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; implication, inducement, estoppel or otherwise. Any license under such
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; intellectual property rights must be express and approved by Intel in
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; writing.
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;
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; Unless otherwise agreed by Intel in writing, you may not remove or
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; alter this notice or any other notice embedded in Materials by Intel
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; or Intel's suppliers or licensors in any way.
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;
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; Example YASM command lines:
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; Windows: yasm -Xvc -f x64 -rnasm -pnasm -o sha256_avx1.obj -g cv8 sha256_avx1.asm
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; Linux: yasm -f x64 -f elf64 -X gnu -g dwarf2 -D LINUX -o sha256_avx1.o sha256_avx1.asm
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;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;
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; This code is described in an Intel White-Paper:
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; "Fast SHA-256 Implementations on Intel Architecture Processors"
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;
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; To find it, surf to http://www.intel.com/p/en_US/embedded
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; and search for that title.
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; The paper is expected to be released roughly at the end of April, 2012
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;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; This code schedules 1 blocks at a time, with 4 lanes per block
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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%define VMOVDQ vmovdqu ;; assume buffers not aligned
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; Define Macros
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; addm [mem], reg
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; Add reg to mem using reg-mem add and store
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%macro addm 2
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add %2, %1
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mov %1, %2
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%endm
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%macro MY_ROR 2
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shld %1,%1,(32-(%2))
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%endm
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; COPY_XMM_AND_BSWAP xmm, [mem], byte_flip_mask
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; Load xmm with mem and byte swap each dword
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%macro COPY_XMM_AND_BSWAP 3
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VMOVDQ %1, %2
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vpshufb %1, %1, %3
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%endmacro
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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%define X0 xmm4
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%define X1 xmm5
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%define X2 xmm6
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%define X3 xmm7
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%define XTMP0 xmm0
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%define XTMP1 xmm1
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%define XTMP2 xmm2
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%define XTMP3 xmm3
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%define XTMP4 xmm8
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%define XFER xmm9
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%define XTMP5 xmm11
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%define SHUF_00BA xmm10 ; shuffle xBxA -> 00BA
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%define SHUF_DC00 xmm12 ; shuffle xDxC -> DC00
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%define BYTE_FLIP_MASK xmm13
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%ifdef LINUX
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%define NUM_BLKS rdx ; 3rd arg
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%define CTX rsi ; 2nd arg
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%define INP rdi ; 1st arg
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%define SRND rdi ; clobbers INP
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%define c ecx
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%define d r8d
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%define e edx
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%else
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%define NUM_BLKS r8 ; 3rd arg
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%define CTX rdx ; 2nd arg
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%define INP rcx ; 1st arg
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%define SRND rcx ; clobbers INP
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%define c edi
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%define d esi
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%define e r8d
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%endif
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%define TBL rbp
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%define a eax
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%define b ebx
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%define f r9d
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%define g r10d
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%define h r11d
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%define y0 r13d
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%define y1 r14d
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%define y2 r15d
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_INP_END_SIZE equ 8
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_INP_SIZE equ 8
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_XFER_SIZE equ 8
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%ifdef LINUX
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_XMM_SAVE_SIZE equ 0
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%else
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_XMM_SAVE_SIZE equ 8*16
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%endif
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; STACK_SIZE plus pushes must be an odd multiple of 8
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_ALIGN_SIZE equ 8
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_INP_END equ 0
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_INP equ _INP_END + _INP_END_SIZE
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_XFER equ _INP + _INP_SIZE
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_XMM_SAVE equ _XFER + _XFER_SIZE + _ALIGN_SIZE
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STACK_SIZE equ _XMM_SAVE + _XMM_SAVE_SIZE
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; rotate_Xs
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; Rotate values of symbols X0...X3
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%macro rotate_Xs 0
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%xdefine X_ X0
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%xdefine X0 X1
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%xdefine X1 X2
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%xdefine X2 X3
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%xdefine X3 X_
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%endm
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; ROTATE_ARGS
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; Rotate values of symbols a...h
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%macro ROTATE_ARGS 0
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%xdefine TMP_ h
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%xdefine h g
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%xdefine g f
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%xdefine f e
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%xdefine e d
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%xdefine d c
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%xdefine c b
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%xdefine b a
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%xdefine a TMP_
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%endm
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%macro FOUR_ROUNDS_AND_SCHED 0
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;; compute s0 four at a time and s1 two at a time
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;; compute W[-16] + W[-7] 4 at a time
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;vmovdqa XTMP0, X3
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mov y0, e ; y0 = e
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MY_ROR y0, (25-11) ; y0 = e >> (25-11)
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mov y1, a ; y1 = a
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vpalignr XTMP0, X3, X2, 4 ; XTMP0 = W[-7]
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MY_ROR y1, (22-13) ; y1 = a >> (22-13)
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xor y0, e ; y0 = e ^ (e >> (25-11))
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mov y2, f ; y2 = f
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MY_ROR y0, (11-6) ; y0 = (e >> (11-6)) ^ (e >> (25-6))
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;vmovdqa XTMP1, X1
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xor y1, a ; y1 = a ^ (a >> (22-13)
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xor y2, g ; y2 = f^g
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vpaddd XTMP0, XTMP0, X0 ; XTMP0 = W[-7] + W[-16]
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xor y0, e ; y0 = e ^ (e >> (11-6)) ^ (e >> (25-6))
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and y2, e ; y2 = (f^g)&e
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MY_ROR y1, (13-2) ; y1 = (a >> (13-2)) ^ (a >> (22-2))
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;; compute s0
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vpalignr XTMP1, X1, X0, 4 ; XTMP1 = W[-15]
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xor y1, a ; y1 = a ^ (a >> (13-2)) ^ (a >> (22-2))
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MY_ROR y0, 6 ; y0 = S1 = (e>>6) & (e>>11) ^ (e>>25)
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xor y2, g ; y2 = CH = ((f^g)&e)^g
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MY_ROR y1, 2 ; y1 = S0 = (a>>2) ^ (a>>13) ^ (a>>22)
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add y2, y0 ; y2 = S1 + CH
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add y2, [rsp + _XFER + 0*4] ; y2 = k + w + S1 + CH
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mov y0, a ; y0 = a
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add h, y2 ; h = h + S1 + CH + k + w
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mov y2, a ; y2 = a
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vpsrld XTMP2, XTMP1, 7
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or y0, c ; y0 = a|c
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add d, h ; d = d + h + S1 + CH + k + w
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and y2, c ; y2 = a&c
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vpslld XTMP3, XTMP1, (32-7)
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and y0, b ; y0 = (a|c)&b
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add h, y1 ; h = h + S1 + CH + k + w + S0
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vpor XTMP3, XTMP3, XTMP2 ; XTMP1 = W[-15] MY_ROR 7
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or y0, y2 ; y0 = MAJ = (a|c)&b)|(a&c)
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add h, y0 ; h = h + S1 + CH + k + w + S0 + MAJ
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ROTATE_ARGS
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mov y0, e ; y0 = e
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mov y1, a ; y1 = a
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MY_ROR y0, (25-11) ; y0 = e >> (25-11)
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xor y0, e ; y0 = e ^ (e >> (25-11))
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mov y2, f ; y2 = f
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MY_ROR y1, (22-13) ; y1 = a >> (22-13)
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vpsrld XTMP2, XTMP1,18
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xor y1, a ; y1 = a ^ (a >> (22-13)
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MY_ROR y0, (11-6) ; y0 = (e >> (11-6)) ^ (e >> (25-6))
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xor y2, g ; y2 = f^g
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vpsrld XTMP4, XTMP1, 3 ; XTMP4 = W[-15] >> 3
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MY_ROR y1, (13-2) ; y1 = (a >> (13-2)) ^ (a >> (22-2))
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xor y0, e ; y0 = e ^ (e >> (11-6)) ^ (e >> (25-6))
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and y2, e ; y2 = (f^g)&e
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MY_ROR y0, 6 ; y0 = S1 = (e>>6) & (e>>11) ^ (e>>25)
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vpslld XTMP1, XTMP1, (32-18)
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xor y1, a ; y1 = a ^ (a >> (13-2)) ^ (a >> (22-2))
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xor y2, g ; y2 = CH = ((f^g)&e)^g
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vpxor XTMP3, XTMP3, XTMP1
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add y2, y0 ; y2 = S1 + CH
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add y2, [rsp + _XFER + 1*4] ; y2 = k + w + S1 + CH
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MY_ROR y1, 2 ; y1 = S0 = (a>>2) ^ (a>>13) ^ (a>>22)
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vpxor XTMP3, XTMP3, XTMP2 ; XTMP1 = W[-15] MY_ROR 7 ^ W[-15] MY_ROR 18
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mov y0, a ; y0 = a
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add h, y2 ; h = h + S1 + CH + k + w
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mov y2, a ; y2 = a
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vpxor XTMP1, XTMP3, XTMP4 ; XTMP1 = s0
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or y0, c ; y0 = a|c
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add d, h ; d = d + h + S1 + CH + k + w
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and y2, c ; y2 = a&c
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;; compute low s1
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vpshufd XTMP2, X3, 11111010b ; XTMP2 = W[-2] {BBAA}
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and y0, b ; y0 = (a|c)&b
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add h, y1 ; h = h + S1 + CH + k + w + S0
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vpaddd XTMP0, XTMP0, XTMP1 ; XTMP0 = W[-16] + W[-7] + s0
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or y0, y2 ; y0 = MAJ = (a|c)&b)|(a&c)
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add h, y0 ; h = h + S1 + CH + k + w + S0 + MAJ
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ROTATE_ARGS
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;vmovdqa XTMP3, XTMP2 ; XTMP3 = W[-2] {BBAA}
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mov y0, e ; y0 = e
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mov y1, a ; y1 = a
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MY_ROR y0, (25-11) ; y0 = e >> (25-11)
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;vmovdqa XTMP4, XTMP2 ; XTMP4 = W[-2] {BBAA}
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xor y0, e ; y0 = e ^ (e >> (25-11))
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MY_ROR y1, (22-13) ; y1 = a >> (22-13)
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mov y2, f ; y2 = f
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xor y1, a ; y1 = a ^ (a >> (22-13)
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MY_ROR y0, (11-6) ; y0 = (e >> (11-6)) ^ (e >> (25-6))
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vpsrld XTMP4, XTMP2, 10 ; XTMP4 = W[-2] >> 10 {BBAA}
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xor y2, g ; y2 = f^g
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vpsrlq XTMP3, XTMP2, 19 ; XTMP3 = W[-2] MY_ROR 19 {xBxA}
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xor y0, e ; y0 = e ^ (e >> (11-6)) ^ (e >> (25-6))
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and y2, e ; y2 = (f^g)&e
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vpsrlq XTMP2, XTMP2, 17 ; XTMP2 = W[-2] MY_ROR 17 {xBxA}
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MY_ROR y1, (13-2) ; y1 = (a >> (13-2)) ^ (a >> (22-2))
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xor y1, a ; y1 = a ^ (a >> (13-2)) ^ (a >> (22-2))
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xor y2, g ; y2 = CH = ((f^g)&e)^g
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MY_ROR y0, 6 ; y0 = S1 = (e>>6) & (e>>11) ^ (e>>25)
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vpxor XTMP2, XTMP2, XTMP3
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add y2, y0 ; y2 = S1 + CH
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MY_ROR y1, 2 ; y1 = S0 = (a>>2) ^ (a>>13) ^ (a>>22)
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add y2, [rsp + _XFER + 2*4] ; y2 = k + w + S1 + CH
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vpxor XTMP4, XTMP4, XTMP2 ; XTMP4 = s1 {xBxA}
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mov y0, a ; y0 = a
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add h, y2 ; h = h + S1 + CH + k + w
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mov y2, a ; y2 = a
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vpshufb XTMP4, XTMP4, SHUF_00BA ; XTMP4 = s1 {00BA}
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or y0, c ; y0 = a|c
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add d, h ; d = d + h + S1 + CH + k + w
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and y2, c ; y2 = a&c
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vpaddd XTMP0, XTMP0, XTMP4 ; XTMP0 = {..., ..., W[1], W[0]}
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and y0, b ; y0 = (a|c)&b
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add h, y1 ; h = h + S1 + CH + k + w + S0
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;; compute high s1
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vpshufd XTMP2, XTMP0, 01010000b ; XTMP2 = W[-2] {DDCC}
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or y0, y2 ; y0 = MAJ = (a|c)&b)|(a&c)
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add h, y0 ; h = h + S1 + CH + k + w + S0 + MAJ
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ROTATE_ARGS
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;vmovdqa XTMP3, XTMP2 ; XTMP3 = W[-2] {DDCC}
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mov y0, e ; y0 = e
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MY_ROR y0, (25-11) ; y0 = e >> (25-11)
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mov y1, a ; y1 = a
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;vmovdqa XTMP5, XTMP2 ; XTMP5 = W[-2] {DDCC}
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MY_ROR y1, (22-13) ; y1 = a >> (22-13)
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xor y0, e ; y0 = e ^ (e >> (25-11))
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mov y2, f ; y2 = f
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MY_ROR y0, (11-6) ; y0 = (e >> (11-6)) ^ (e >> (25-6))
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vpsrld XTMP5, XTMP2, 10 ; XTMP5 = W[-2] >> 10 {DDCC}
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xor y1, a ; y1 = a ^ (a >> (22-13)
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xor y2, g ; y2 = f^g
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vpsrlq XTMP3, XTMP2, 19 ; XTMP3 = W[-2] MY_ROR 19 {xDxC}
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xor y0, e ; y0 = e ^ (e >> (11-6)) ^ (e >> (25-6))
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and y2, e ; y2 = (f^g)&e
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MY_ROR y1, (13-2) ; y1 = (a >> (13-2)) ^ (a >> (22-2))
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vpsrlq XTMP2, XTMP2, 17 ; XTMP2 = W[-2] MY_ROR 17 {xDxC}
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xor y1, a ; y1 = a ^ (a >> (13-2)) ^ (a >> (22-2))
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MY_ROR y0, 6 ; y0 = S1 = (e>>6) & (e>>11) ^ (e>>25)
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xor y2, g ; y2 = CH = ((f^g)&e)^g
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vpxor XTMP2, XTMP2, XTMP3
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MY_ROR y1, 2 ; y1 = S0 = (a>>2) ^ (a>>13) ^ (a>>22)
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add y2, y0 ; y2 = S1 + CH
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add y2, [rsp + _XFER + 3*4] ; y2 = k + w + S1 + CH
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vpxor XTMP5, XTMP5, XTMP2 ; XTMP5 = s1 {xDxC}
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mov y0, a ; y0 = a
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add h, y2 ; h = h + S1 + CH + k + w
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mov y2, a ; y2 = a
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vpshufb XTMP5, XTMP5, SHUF_DC00 ; XTMP5 = s1 {DC00}
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or y0, c ; y0 = a|c
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add d, h ; d = d + h + S1 + CH + k + w
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and y2, c ; y2 = a&c
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vpaddd X0, XTMP5, XTMP0 ; X0 = {W[3], W[2], W[1], W[0]}
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and y0, b ; y0 = (a|c)&b
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add h, y1 ; h = h + S1 + CH + k + w + S0
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or y0, y2 ; y0 = MAJ = (a|c)&b)|(a&c)
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add h, y0 ; h = h + S1 + CH + k + w + S0 + MAJ
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ROTATE_ARGS
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rotate_Xs
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%endm
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;; input is [rsp + _XFER + %1 * 4]
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%macro DO_ROUND 1
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mov y0, e ; y0 = e
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MY_ROR y0, (25-11) ; y0 = e >> (25-11)
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mov y1, a ; y1 = a
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xor y0, e ; y0 = e ^ (e >> (25-11))
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MY_ROR y1, (22-13) ; y1 = a >> (22-13)
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mov y2, f ; y2 = f
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xor y1, a ; y1 = a ^ (a >> (22-13)
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MY_ROR y0, (11-6) ; y0 = (e >> (11-6)) ^ (e >> (25-6))
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xor y2, g ; y2 = f^g
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xor y0, e ; y0 = e ^ (e >> (11-6)) ^ (e >> (25-6))
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MY_ROR y1, (13-2) ; y1 = (a >> (13-2)) ^ (a >> (22-2))
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and y2, e ; y2 = (f^g)&e
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xor y1, a ; y1 = a ^ (a >> (13-2)) ^ (a >> (22-2))
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MY_ROR y0, 6 ; y0 = S1 = (e>>6) & (e>>11) ^ (e>>25)
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xor y2, g ; y2 = CH = ((f^g)&e)^g
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add y2, y0 ; y2 = S1 + CH
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MY_ROR y1, 2 ; y1 = S0 = (a>>2) ^ (a>>13) ^ (a>>22)
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add y2, [rsp + _XFER + %1 * 4] ; y2 = k + w + S1 + CH
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mov y0, a ; y0 = a
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add h, y2 ; h = h + S1 + CH + k + w
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mov y2, a ; y2 = a
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or y0, c ; y0 = a|c
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add d, h ; d = d + h + S1 + CH + k + w
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and y2, c ; y2 = a&c
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and y0, b ; y0 = (a|c)&b
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add h, y1 ; h = h + S1 + CH + k + w + S0
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or y0, y2 ; y0 = MAJ = (a|c)&b)|(a&c)
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add h, y0 ; h = h + S1 + CH + k + w + S0 + MAJ
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ROTATE_ARGS
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%endm
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; void sha256_avx(void *input_data, UINT32 digest[8], UINT64 num_blks)
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;; arg 1 : pointer to input data
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;; arg 2 : pointer to digest
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;; arg 3 : Num blocks
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section .text
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global sha256_avx
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align 32
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sha256_avx:
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push rbx
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%ifndef LINUX
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push rsi
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push rdi
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%endif
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push rbp
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push r13
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push r14
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push r15
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sub rsp,STACK_SIZE
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%ifndef LINUX
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vmovdqa [rsp + _XMM_SAVE + 0*16],xmm6
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vmovdqa [rsp + _XMM_SAVE + 1*16],xmm7
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vmovdqa [rsp + _XMM_SAVE + 2*16],xmm8
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vmovdqa [rsp + _XMM_SAVE + 3*16],xmm9
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vmovdqa [rsp + _XMM_SAVE + 4*16],xmm10
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vmovdqa [rsp + _XMM_SAVE + 5*16],xmm11
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vmovdqa [rsp + _XMM_SAVE + 6*16],xmm12
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vmovdqa [rsp + _XMM_SAVE + 7*16],xmm13
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%endif
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shl NUM_BLKS, 6 ; convert to bytes
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jz done_hash
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add NUM_BLKS, INP ; pointer to end of data
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mov [rsp + _INP_END], NUM_BLKS
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;; load initial digest
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mov a,[4*0 + CTX]
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mov b,[4*1 + CTX]
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mov c,[4*2 + CTX]
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mov d,[4*3 + CTX]
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mov e,[4*4 + CTX]
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mov f,[4*5 + CTX]
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mov g,[4*6 + CTX]
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mov h,[4*7 + CTX]
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vmovdqa BYTE_FLIP_MASK, [PSHUFFLE_BYTE_FLIP_MASK wrt rip]
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vmovdqa SHUF_00BA, [_SHUF_00BA wrt rip]
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vmovdqa SHUF_DC00, [_SHUF_DC00 wrt rip]
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loop0:
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lea TBL,[K256 wrt rip]
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;; byte swap first 16 dwords
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COPY_XMM_AND_BSWAP X0, [INP + 0*16], BYTE_FLIP_MASK
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COPY_XMM_AND_BSWAP X1, [INP + 1*16], BYTE_FLIP_MASK
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COPY_XMM_AND_BSWAP X2, [INP + 2*16], BYTE_FLIP_MASK
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COPY_XMM_AND_BSWAP X3, [INP + 3*16], BYTE_FLIP_MASK
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mov [rsp + _INP], INP
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;; schedule 48 input dwords, by doing 3 rounds of 16 each
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mov SRND, 3
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align 16
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loop1:
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vpaddd XFER, X0, [TBL + 0*16]
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vmovdqa [rsp + _XFER], XFER
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FOUR_ROUNDS_AND_SCHED
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vpaddd XFER, X0, [TBL + 1*16]
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vmovdqa [rsp + _XFER], XFER
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FOUR_ROUNDS_AND_SCHED
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vpaddd XFER, X0, [TBL + 2*16]
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vmovdqa [rsp + _XFER], XFER
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FOUR_ROUNDS_AND_SCHED
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vpaddd XFER, X0, [TBL + 3*16]
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vmovdqa [rsp + _XFER], XFER
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add TBL, 4*16
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FOUR_ROUNDS_AND_SCHED
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sub SRND, 1
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jne loop1
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mov SRND, 2
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loop2:
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vpaddd XFER, X0, [TBL + 0*16]
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vmovdqa [rsp + _XFER], XFER
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DO_ROUND 0
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DO_ROUND 1
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DO_ROUND 2
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DO_ROUND 3
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vpaddd XFER, X1, [TBL + 1*16]
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vmovdqa [rsp + _XFER], XFER
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add TBL, 2*16
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DO_ROUND 0
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DO_ROUND 1
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DO_ROUND 2
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DO_ROUND 3
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vmovdqa X0, X2
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vmovdqa X1, X3
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sub SRND, 1
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jne loop2
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addm [4*0 + CTX],a
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addm [4*1 + CTX],b
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addm [4*2 + CTX],c
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addm [4*3 + CTX],d
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addm [4*4 + CTX],e
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addm [4*5 + CTX],f
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addm [4*6 + CTX],g
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addm [4*7 + CTX],h
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mov INP, [rsp + _INP]
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add INP, 64
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cmp INP, [rsp + _INP_END]
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jne loop0
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done_hash:
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%ifndef LINUX
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vmovdqa xmm6,[rsp + _XMM_SAVE + 0*16]
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vmovdqa xmm7,[rsp + _XMM_SAVE + 1*16]
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vmovdqa xmm8,[rsp + _XMM_SAVE + 2*16]
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vmovdqa xmm9,[rsp + _XMM_SAVE + 3*16]
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vmovdqa xmm10,[rsp + _XMM_SAVE + 4*16]
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vmovdqa xmm11,[rsp + _XMM_SAVE + 5*16]
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vmovdqa xmm12,[rsp + _XMM_SAVE + 6*16]
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vmovdqa xmm13,[rsp + _XMM_SAVE + 7*16]
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%endif
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add rsp, STACK_SIZE
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pop r15
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pop r14
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pop r13
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pop rbp
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%ifndef LINUX
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pop rdi
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pop rsi
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%endif
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pop rbx
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ret
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section .data
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align 64
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K256:
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dd 0x428a2f98,0x71374491,0xb5c0fbcf,0xe9b5dba5
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dd 0x3956c25b,0x59f111f1,0x923f82a4,0xab1c5ed5
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dd 0xd807aa98,0x12835b01,0x243185be,0x550c7dc3
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dd 0x72be5d74,0x80deb1fe,0x9bdc06a7,0xc19bf174
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dd 0xe49b69c1,0xefbe4786,0x0fc19dc6,0x240ca1cc
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dd 0x2de92c6f,0x4a7484aa,0x5cb0a9dc,0x76f988da
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dd 0x983e5152,0xa831c66d,0xb00327c8,0xbf597fc7
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dd 0xc6e00bf3,0xd5a79147,0x06ca6351,0x14292967
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dd 0x27b70a85,0x2e1b2138,0x4d2c6dfc,0x53380d13
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dd 0x650a7354,0x766a0abb,0x81c2c92e,0x92722c85
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dd 0xa2bfe8a1,0xa81a664b,0xc24b8b70,0xc76c51a3
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dd 0xd192e819,0xd6990624,0xf40e3585,0x106aa070
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dd 0x19a4c116,0x1e376c08,0x2748774c,0x34b0bcb5
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dd 0x391c0cb3,0x4ed8aa4a,0x5b9cca4f,0x682e6ff3
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dd 0x748f82ee,0x78a5636f,0x84c87814,0x8cc70208
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dd 0x90befffa,0xa4506ceb,0xbef9a3f7,0xc67178f2
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PSHUFFLE_BYTE_FLIP_MASK: ddq 0x0c0d0e0f08090a0b0405060700010203
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; shuffle xBxA -> 00BA
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_SHUF_00BA: ddq 0xFFFFFFFFFFFFFFFF0b0a090803020100
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; shuffle xDxC -> DC00
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_SHUF_DC00: ddq 0x0b0a090803020100FFFFFFFFFFFFFFFF
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