154 lines
6.2 KiB
C
154 lines
6.2 KiB
C
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/*
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* wterl: an Erlang NIF for WiredTiger
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*
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* Copyright (c) 2012-2013 Basho Technologies, Inc. All Rights Reserved.
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*
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* This file is provided to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at:
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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*/
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/*
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* Most of the following source code is copied directly from: "The Lock-Free
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* Library" (http://www.cl.cam.ac.uk/research/srg/netos/lock-free/) reused and
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* redistrubuted in accordance with their license:
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*
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* Copyright (c) 2002-2003 K A Fraser, All Rights Reserved.
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*
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* * Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* * Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* * The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
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* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __CAS_H_
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#define __CAS_H_
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#define CACHE_LINE_SIZE 64
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#define ATOMIC_ADD_TO(_v,_x) \
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do { \
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int __val = (_v), __newval; \
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while ( (__newval = CASIO(&(_v),__val,__val+(_x))) != __val ) \
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__val = __newval; \
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} while ( 0 )
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#define ATOMIC_SET_TO(_v,_x) \
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do { \
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int __val = (_v), __newval; \
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while ( (__newval = CASIO(&(_v),__val,__val=(_x))) != __val ) \
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__val = __newval; \
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} while ( 0 )
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#define ALIGNED_ENIF_ALLOC(_s) \
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((void *)(((unsigned long)enif_alloc((_s)+CACHE_LINE_SIZE*2) + \
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CACHE_LINE_SIZE - 1) & ~(CACHE_LINE_SIZE-1))) \
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/*
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* I. Compare-and-swap.
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*/
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/*
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* This is a strong barrier! Reads cannot be delayed beyond a later store.
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* Reads cannot be hoisted beyond a LOCK prefix. Stores always in-order.
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*/
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#define CAS(_a, _o, _n) \
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({ __typeof__(_o) __o = _o; \
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__asm__ __volatile__( \
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"lock cmpxchg %3,%1" \
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: "=a" (__o), "=m" (*(volatile unsigned int *)(_a)) \
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: "0" (__o), "r" (_n) ); \
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__o; \
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})
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#define FAS(_a, _n) \
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({ __typeof__(_n) __o; \
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__asm__ __volatile__( \
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"lock xchg %0,%1" \
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: "=r" (__o), "=m" (*(volatile unsigned int *)(_a)) \
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: "0" (_n) ); \
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__o; \
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})
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#define CAS64(_a, _o, _n) \
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({ __typeof__(_o) __o = _o; \
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__asm__ __volatile__( \
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"movl %3, %%ecx;" \
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"movl %4, %%ebx;" \
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"lock cmpxchg8b %1" \
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: "=A" (__o), "=m" (*(volatile unsigned long long *)(_a)) \
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: "0" (__o), "m" (_n >> 32), "m" (_n) \
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: "ebx", "ecx" ); \
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__o; \
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})
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/* Update Integer location, return Old value. */
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#define CASIO CAS
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#define FASIO FAS
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/* Update Pointer location, return Old value. */
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#define CASPO CAS
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#define FASPO FAS
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/* Update 32/64-bit location, return Old value. */
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#define CAS32O CAS
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#define CAS64O CAS64
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/*
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* II. Memory barriers.
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* WMB(): All preceding write operations must commit before any later writes.
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* RMB(): All preceding read operations must commit before any later reads.
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* MB(): All preceding memory accesses must commit before any later accesses.
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*
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* If the compiler does not observe these barriers (but any sane compiler
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* will!), then VOLATILE should be defined as 'volatile'.
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*/
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#define MB() __asm__ __volatile__ ("lock; addl $0,0(%%esp)" : : : "memory")
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#define WMB() __asm__ __volatile__ ("" : : : "memory")
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#define RMB() MB()
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#define VOLATILE /*volatile*/
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/* On Intel, CAS is a strong barrier, but not a compile barrier. */
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#define RMB_NEAR_CAS() WMB()
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#define WMB_NEAR_CAS() WMB()
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#define MB_NEAR_CAS() WMB()
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/*
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* III. Cycle counter access.
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*/
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typedef unsigned long long tick_t;
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#define RDTICK() \
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({ tick_t __t; __asm__ __volatile__ ("rdtsc" : "=A" (__t)); __t; })
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#endif /* __CAS_H_ */
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