2007-08-27 22:53:31 +00:00
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// See MultiProcessor Specification Version 1.[14]
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2006-06-22 01:28:57 +00:00
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2006-09-06 17:50:20 +00:00
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struct mp { // floating pointer
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uchar signature[4]; // "_MP_"
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2006-09-06 19:08:14 +00:00
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void *physaddr; // phys addr of MP config table
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2006-09-06 17:50:20 +00:00
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uchar length; // 1
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uchar specrev; // [14]
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uchar checksum; // all bytes must add up to 0
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2006-09-06 19:08:14 +00:00
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uchar type; // MP system config type
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2006-07-20 09:07:53 +00:00
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uchar imcrp;
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uchar reserved[3];
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2006-06-21 01:53:07 +00:00
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};
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2007-08-27 22:53:31 +00:00
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struct mpconf { // configuration table header
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2006-09-06 17:50:20 +00:00
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uchar signature[4]; // "PCMP"
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ushort length; // total table length
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uchar version; // [14]
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uchar checksum; // all bytes must add up to 0
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uchar product[20]; // product id
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2006-09-06 19:08:14 +00:00
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uint *oemtable; // OEM table pointer
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2006-09-06 17:50:20 +00:00
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ushort oemlength; // OEM table length
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ushort entry; // entry count
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2006-09-06 19:08:14 +00:00
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uint *lapicaddr; // address of local APIC
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2006-09-06 17:50:20 +00:00
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ushort xlength; // extended table length
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uchar xchecksum; // extended table checksum
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2006-07-20 09:07:53 +00:00
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uchar reserved;
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2006-06-21 01:53:07 +00:00
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};
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2007-08-27 22:53:31 +00:00
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struct mpproc { // processor table entry
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2006-09-06 17:50:20 +00:00
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uchar type; // entry type (0)
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uchar apicid; // local APIC id
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uchar version; // local APIC verison
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uchar flags; // CPU flags
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2007-08-27 22:53:31 +00:00
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#define MPBOOT 0x02 // This proc is the bootstrap processor.
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2006-09-06 17:50:20 +00:00
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uchar signature[4]; // CPU signature
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uint feature; // feature flags from CPUID instruction
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2006-07-20 09:07:53 +00:00
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uchar reserved[8];
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2006-06-21 01:53:07 +00:00
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};
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2006-09-06 17:50:20 +00:00
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struct mpioapic { // I/O APIC table entry
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uchar type; // entry type (2)
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uchar apicno; // I/O APIC id
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uchar version; // I/O APIC version
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uchar flags; // I/O APIC flags
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uint *addr; // I/O APIC address
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2006-06-21 01:53:07 +00:00
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};
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2007-08-27 22:53:31 +00:00
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// Table entry types
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#define MPPROC 0x00 // One per processor
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#define MPBUS 0x01 // One per bus
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#define MPIOAPIC 0x02 // One per I/O APIC
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#define MPIOINTR 0x03 // One per bus interrupt source
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#define MPLINTR 0x04 // One per system interrupt source
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2006-06-22 01:28:57 +00:00
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