85 lines
2 KiB
C
85 lines
2 KiB
C
#include "types.h"
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#include "mp.h"
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#include "defs.h"
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#include "x86.h"
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#include "traps.h"
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#include "ioapic.h"
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struct ioapic {
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uint ioregsel; uint p01; uint p02; uint p03;
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uint iowin; uint p11; uint p12; uint p13;
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};
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#define IOAPIC_REDTBL_LO(i) (IOAPIC_REDTBL + (i) * 2)
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#define IOAPIC_REDTBL_HI(i) (IOAPIC_REDTBL_LO(i) + 1)
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static uint
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ioapic_read(struct ioapic *io, int reg)
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{
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io->ioregsel = reg;
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return io->iowin;
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}
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static void
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ioapic_write(struct ioapic *io, int reg, uint val)
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{
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io->ioregsel = reg;
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io->iowin = val;
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}
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void
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ioapic_init(void)
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{
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struct ioapic *io;
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uint l, h;
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int nintr;
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uchar id;
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int i;
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if(!ismp)
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return;
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io = (struct ioapic*) IO_APIC_BASE;
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l = ioapic_read(io, IOAPIC_VER);
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nintr = ((l & IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) + 1;
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id = ioapic_read(io, IOAPIC_ID) >> APIC_ID_SHIFT;
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if(id != ioapic_id)
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cprintf("ioapic_init: id isn't equal to ioapic_id; not a MP\n");
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for(i = 0; i < nintr; i++) {
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// active-hi and edge-triggered for ISA interrupts
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// Assume that pin 0 on the first I/O APIC is an ExtINT pin.
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// Assume that pins 1-15 are ISA interrupts
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l = ioapic_read(io, IOAPIC_REDTBL_LO(i));
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l = l & ~IOART_INTMASK; // allow INTs
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l |= IOART_INTMSET;
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l = l & ~IOART_INTPOL; // active hi
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l = l & ~IOART_TRGRMOD; // edgee triggered
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l = l & ~IOART_DELMOD; // fixed
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l = l & ~IOART_DESTMOD; // physical mode
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l = l | (IRQ_OFFSET + i); // vector
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ioapic_write(io, IOAPIC_REDTBL_LO(i), l);
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h = ioapic_read(io, IOAPIC_REDTBL_HI(i));
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h &= ~IOART_DEST;
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ioapic_write(io, IOAPIC_REDTBL_HI(i), h);
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}
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}
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void
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ioapic_enable (int irq, int cpunum)
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{
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uint l, h;
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struct ioapic *io;
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if(!ismp)
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return;
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io = (struct ioapic*) IO_APIC_BASE;
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l = ioapic_read(io, IOAPIC_REDTBL_LO(irq));
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l = l & ~IOART_INTMASK; // allow INTs
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ioapic_write(io, IOAPIC_REDTBL_LO(irq), l);
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h = ioapic_read(io, IOAPIC_REDTBL_HI(irq));
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h &= ~IOART_DEST;
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h |= (cpunum << APIC_ID_SHIFT);
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ioapic_write(io, IOAPIC_REDTBL_HI(irq), h);
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}
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