5ce9751cab
Linux 2.4 box using gcc 3.4.6 don't seem to follow the same
conventions as the i386-jos-elf-gcc compilers.
Can run make 'TOOLPREFIX=' or edit the Makefile.
curproc[cpu()] can now be NULL, indicating that no proc is running.
This seemed safer to me than having curproc[0] and curproc[1]
both pointing at proc[0] potentially.
The old implementation of swtch depended on the stack frame layout
used inside swtch being okay to return from on the other stack
(exactly the V6 you are not expected to understand this).
It also could be called in two contexts: at boot time, to schedule
the very first process, and later, on behalf of a process, to sleep
or schedule some other process.
I split this into two functions: scheduler and swtch.
The scheduler is now a separate never-returning function, invoked
by each cpu once set up. The scheduler looks like:
scheduler() {
setjmp(cpu.context);
pick proc to schedule
blah blah blah
longjmp(proc.context)
}
The new swtch is intended to be called only when curproc[cpu()] is not NULL,
that is, only on behalf of a user proc. It does:
swtch() {
if(setjmp(proc.context) == 0)
longjmp(cpu.context)
}
to save the current proc context and then jump over to the scheduler,
running on the cpu stack.
Similarly the system call stubs are now in assembly in usys.S to avoid
needing to know the details of stack frame layout used by the compiler.
Also various changes in the debugging prints.
405 lines
10 KiB
C
405 lines
10 KiB
C
#include "types.h"
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#include "mp.h"
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#include "defs.h"
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#include "memlayout.h"
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#include "param.h"
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#include "x86.h"
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#include "traps.h"
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#include "mmu.h"
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#include "proc.h"
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/*
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* Credit: Plan 9 sources, Intel MP spec, and Cliff Frey
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*/
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enum { /* Local APIC registers */
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LAPIC_ID = 0x0020, /* ID */
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LAPIC_VER = 0x0030, /* Version */
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LAPIC_TPR = 0x0080, /* Task Priority */
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LAPIC_APR = 0x0090, /* Arbitration Priority */
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LAPIC_PPR = 0x00A0, /* Processor Priority */
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LAPIC_EOI = 0x00B0, /* EOI */
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LAPIC_LDR = 0x00D0, /* Logical Destination */
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LAPIC_DFR = 0x00E0, /* Destination Format */
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LAPIC_SVR = 0x00F0, /* Spurious Interrupt Vector */
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LAPIC_ISR = 0x0100, /* Interrupt Status (8 registers) */
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LAPIC_TMR = 0x0180, /* Trigger Mode (8 registers) */
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LAPIC_IRR = 0x0200, /* Interrupt Request (8 registers) */
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LAPIC_ESR = 0x0280, /* Error Status */
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LAPIC_ICRLO = 0x0300, /* Interrupt Command */
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LAPIC_ICRHI = 0x0310, /* Interrupt Command [63:32] */
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LAPIC_TIMER = 0x0320, /* Local Vector Table 0 (TIMER) */
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LAPIC_PCINT = 0x0340, /* Performance Counter LVT */
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LAPIC_LINT0 = 0x0350, /* Local Vector Table 1 (LINT0) */
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LAPIC_LINT1 = 0x0360, /* Local Vector Table 2 (LINT1) */
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LAPIC_ERROR = 0x0370, /* Local Vector Table 3 (ERROR) */
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LAPIC_TICR = 0x0380, /* Timer Initial Count */
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LAPIC_TCCR = 0x0390, /* Timer Current Count */
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LAPIC_TDCR = 0x03E0, /* Timer Divide Configuration */
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};
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enum { /* LAPIC_SVR */
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LAPIC_ENABLE = 0x00000100, /* Unit Enable */
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LAPIC_FOCUS = 0x00000200, /* Focus Processor Checking Disable */
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};
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enum { /* LAPIC_ICRLO */
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/* [14] IPI Trigger Mode Level (RW) */
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LAPIC_DEASSERT = 0x00000000, /* Deassert level-sensitive interrupt */
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LAPIC_ASSERT = 0x00004000, /* Assert level-sensitive interrupt */
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/* [17:16] Remote Read Status */
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LAPIC_INVALID = 0x00000000, /* Invalid */
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LAPIC_WAIT = 0x00010000, /* In-Progress */
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LAPIC_VALID = 0x00020000, /* Valid */
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/* [19:18] Destination Shorthand */
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LAPIC_FIELD = 0x00000000, /* No shorthand */
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LAPIC_SELF = 0x00040000, /* Self is single destination */
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LAPIC_ALLINC = 0x00080000, /* All including self */
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LAPIC_ALLEXC = 0x000C0000, /* All Excluding self */
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};
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enum { /* LAPIC_ESR */
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LAPIC_SENDCS = 0x00000001, /* Send CS Error */
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LAPIC_RCVCS = 0x00000002, /* Receive CS Error */
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LAPIC_SENDACCEPT = 0x00000004, /* Send Accept Error */
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LAPIC_RCVACCEPT = 0x00000008, /* Receive Accept Error */
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LAPIC_SENDVECTOR = 0x00000020, /* Send Illegal Vector */
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LAPIC_RCVVECTOR = 0x00000040, /* Receive Illegal Vector */
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LAPIC_REGISTER = 0x00000080, /* Illegal Register Address */
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};
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enum { /* LAPIC_TIMER */
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/* [17] Timer Mode (RW) */
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LAPIC_ONESHOT = 0x00000000, /* One-shot */
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LAPIC_PERIODIC = 0x00020000, /* Periodic */
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/* [19:18] Timer Base (RW) */
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LAPIC_CLKIN = 0x00000000, /* use CLKIN as input */
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LAPIC_TMBASE = 0x00040000, /* use TMBASE */
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LAPIC_DIVIDER = 0x00080000, /* use output of the divider */
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};
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enum { /* LAPIC_TDCR */
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LAPIC_X2 = 0x00000000, /* divide by 2 */
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LAPIC_X4 = 0x00000001, /* divide by 4 */
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LAPIC_X8 = 0x00000002, /* divide by 8 */
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LAPIC_X16 = 0x00000003, /* divide by 16 */
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LAPIC_X32 = 0x00000008, /* divide by 32 */
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LAPIC_X64 = 0x00000009, /* divide by 64 */
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LAPIC_X128 = 0x0000000A, /* divide by 128 */
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LAPIC_X1 = 0x0000000B, /* divide by 1 */
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};
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static char* buses[] = {
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"CBUSI ",
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"CBUSII",
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"EISA ",
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"FUTURE",
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"INTERN",
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"ISA ",
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"MBI ",
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"MBII ",
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"MCA ",
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"MPI ",
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"MPSA ",
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"NUBUS ",
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"PCI ",
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"PCMCIA",
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"TC ",
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"VL ",
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"VME ",
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"XPRESS",
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0,
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};
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#define APBOOTCODE 0x7000 // XXX hack
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static struct MP* mp; // The MP floating point structure
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static uint32_t *lapicaddr;
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struct cpu cpus[NCPU];
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int ncpu;
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static struct cpu *bcpu;
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static int
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lapic_read(int r)
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{
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return *(lapicaddr+(r/sizeof(*lapicaddr)));
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}
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static void
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lapic_write(int r, int data)
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{
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*(lapicaddr+(r/sizeof(*lapicaddr))) = data;
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}
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void
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lapic_timerinit()
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{
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cprintf("%d: init timer\n", cpu());
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lapic_write(LAPIC_TDCR, LAPIC_X1);
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lapic_write(LAPIC_TIMER, LAPIC_CLKIN | LAPIC_PERIODIC | (IRQ_OFFSET + IRQ_TIMER));
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lapic_write(LAPIC_TCCR, 10000000);
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lapic_write(LAPIC_TICR, 10000000);
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}
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void
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lapic_timerintr()
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{
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cprintf("%d: timer interrupt!\n", cpu());
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lapic_write (LAPIC_EOI, 0);
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}
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void
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lapic_init(int c)
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{
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uint32_t r, lvt;
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cprintf("lapic_init %d\n", c);
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lapic_write(LAPIC_DFR, 0xFFFFFFFF); // set destination format register
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r = (lapic_read(LAPIC_ID)>>24) & 0xFF; // read APIC ID
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lapic_write(LAPIC_LDR, (1<<r)<<24); // set logical destination register to r
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lapic_write(LAPIC_TPR, 0xFF); // no interrupts for now
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lapic_write(LAPIC_SVR, LAPIC_ENABLE|(IRQ_OFFSET+IRQ_SPURIOUS)); // enable APIC
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// in virtual wire mode, set up the LINT0 and LINT1 as follows:
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lapic_write(LAPIC_LINT0, APIC_IMASK | APIC_EXTINT);
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lapic_write(LAPIC_LINT1, APIC_IMASK | APIC_NMI);
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lapic_write(LAPIC_EOI, 0); // acknowledge any outstanding interrupts.
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lvt = (lapic_read(LAPIC_VER)>>16) & 0xFF;
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if(lvt >= 4)
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lapic_write(LAPIC_PCINT, APIC_IMASK);
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lapic_write(LAPIC_ERROR, IRQ_OFFSET+IRQ_ERROR);
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lapic_write(LAPIC_ESR, 0);
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lapic_read(LAPIC_ESR);
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/*
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* Issue an INIT Level De-Assert to synchronise arbitration ID's.
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*/
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lapic_write(LAPIC_ICRHI, 0);
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lapic_write(LAPIC_ICRLO, LAPIC_ALLINC|APIC_LEVEL|LAPIC_DEASSERT|APIC_INIT);
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while(lapic_read(LAPIC_ICRLO) & APIC_DELIVS)
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;
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cprintf("Done init of an apic\n");
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}
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void
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lapic_enableintr(void)
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{
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lapic_write(LAPIC_TPR, 0);
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}
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void
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lapic_disableintr(void)
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{
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lapic_write(LAPIC_TPR, 0xFF);
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}
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int
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cpu(void)
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{
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return (lapic_read(LAPIC_ID)>>24) & 0xFF;
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}
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static void
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lapic_startap(struct cpu *c, int v)
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{
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int crhi, i;
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volatile int j = 0;
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crhi = c->apicid<<24;
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lapic_write(LAPIC_ICRHI, crhi);
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lapic_write(LAPIC_ICRLO, LAPIC_FIELD|APIC_LEVEL|LAPIC_ASSERT|APIC_INIT);
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while (j++ < 10000) {;}
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lapic_write(LAPIC_ICRLO, LAPIC_FIELD|APIC_LEVEL|LAPIC_DEASSERT|APIC_INIT);
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while (j++ < 1000000) {;}
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// in p9 code, this was i < 2, which is what the spec says on page B-3
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for(i = 0; i < 1; i++){
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lapic_write(LAPIC_ICRHI, crhi);
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lapic_write(LAPIC_ICRLO, LAPIC_FIELD|APIC_EDGE|APIC_STARTUP|(v/PGSIZE));
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while (j++ < 100000) {;}
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}
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}
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static struct MP*
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mp_scan(uint8_t *addr, int len)
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{
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uint8_t *e, *p, sum;
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int i;
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cprintf("scanning: 0x%x\n", (uint32_t)addr);
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e = addr+len;
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for(p = addr; p < e; p += sizeof(struct MP)){
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if(memcmp(p, "_MP_", 4))
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continue;
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sum = 0;
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for(i = 0; i < sizeof(struct MP); i++)
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sum += p[i];
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if(sum == 0)
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return (struct MP *)p;
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}
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return 0;
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}
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static struct MP*
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mp_search(void)
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{
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uint8_t *bda;
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uint32_t p;
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struct MP *mp;
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/*
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* Search for the MP Floating Pointer Structure, which according to the
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* spec is in one of the following three locations:
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* 1) in the first KB of the EBDA;
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* 2) in the last KB of system base memory;
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* 3) in the BIOS ROM between 0xE0000 and 0xFFFFF.
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*/
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bda = (uint8_t*) 0x400;
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if((p = (bda[0x0F]<<8)|bda[0x0E])){
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if((mp = mp_scan((uint8_t*) p, 1024)))
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return mp;
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}
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else{
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p = ((bda[0x14]<<8)|bda[0x13])*1024;
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if((mp = mp_scan((uint8_t*)p-1024, 1024)))
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return mp;
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}
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return mp_scan((uint8_t*)0xF0000, 0x10000);
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}
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static int
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mp_detect(void)
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{
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struct MPCTB *pcmp;
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uint8_t *p, sum;
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uint32_t length;
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/*
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* Search for an MP configuration table. For now,
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* don't accept the default configurations (physaddr == 0).
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* Check for correct signature, calculate the checksum and,
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* if correct, check the version.
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* To do: check extended table checksum.
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*/
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if((mp = mp_search()) == 0 || mp->physaddr == 0)
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return 1;
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pcmp = (struct MPCTB *) mp->physaddr;
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if(memcmp(pcmp, "PCMP", 4))
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return 2;
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length = pcmp->length;
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sum = 0;
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for(p = (uint8_t*)pcmp; length; length--)
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sum += *p++;
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if(sum || (pcmp->version != 1 && pcmp->version != 4))
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return 3;
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cprintf("Mp spec rev #: %x imcrp 0x%x\n", mp->specrev, mp->imcrp);
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return 0;
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}
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int
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mp_isbcpu()
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{
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if (bcpu == 0) return 1;
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else return 0;
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}
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void
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mp_init()
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{
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int r;
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uint8_t *p, *e;
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struct MPCTB *mpctb;
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struct MPPE *proc;
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struct MPBE *bus;
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int c;
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extern int main();
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int i;
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ncpu = 0;
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if ((r = mp_detect()) != 0) return;
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cprintf ("This computer is a multiprocessor!\n");
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/*
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* Run through the table saving information needed for starting
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* application processors and initialising any I/O APICs. The table
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* is guaranteed to be in order such that only one pass is necessary.
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*/
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mpctb = (struct MPCTB *) mp->physaddr;
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lapicaddr = (uint32_t *) mpctb->lapicaddr;
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cprintf("apicaddr: %x\n", lapicaddr);
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p = ((uint8_t*)mpctb)+sizeof(struct MPCTB);
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e = ((uint8_t*)mpctb)+mpctb->length;
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while(p < e) {
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switch(*p){
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case MPPROCESSOR:
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proc = (struct MPPE *) p;
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cpus[ncpu].apicid = proc->apicid;
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cprintf("a processor %x\n", cpus[ncpu].apicid);
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if (proc->flags & MPBP) {
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bcpu = &cpus[ncpu];
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}
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ncpu++;
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p += sizeof(struct MPPE);
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continue;
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case MPBUS:
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bus = (struct MPBE *) p;
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for(i = 0; buses[i]; i++){
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if(strncmp(buses[i], bus->string, sizeof(bus->string)) == 0)
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break;
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}
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cprintf("a bus %d\n", i);
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p += sizeof(struct MPBE);
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continue;
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case MPIOAPIC:
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cprintf("an I/O APIC\n");
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p += sizeof(struct MPIOAPIC);
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continue;
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case MPIOINTR:
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cprintf("an I/O intr\n");
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p += sizeof(struct MPIE);
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continue;
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default:
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cprintf("mpinit: unknown PCMP type 0x%x (e-p 0x%x)\n", *p, e-p);
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while(p < e){
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cprintf("%uX ", *p);
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p++;
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}
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break;
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}
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}
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lapic_init(bcpu-cpus);
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cprintf("ncpu: %d boot %d\n", ncpu, bcpu-cpus);
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extern uint8_t _binary_bootother_start[], _binary_bootother_size[];
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memmove((void *) APBOOTCODE,_binary_bootother_start,
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(uint32_t) _binary_bootother_size);
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acquire_spinlock(&kernel_lock);
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for(c = 0; c < ncpu; c++){
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if (cpus+c == bcpu) continue;
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cprintf ("starting processor %d\n", c);
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release_grant_spinlock(&kernel_lock, c);
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*(unsigned *)(APBOOTCODE-4) = (unsigned) (cpus[c].mpstack) + MPSTACK; // tell it what to use for %esp
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*(unsigned *)(APBOOTCODE-8) = (unsigned)&main; // tell it where to jump to
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lapic_startap(cpus + c, (uint32_t) APBOOTCODE);
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acquire_spinlock(&kernel_lock);
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cprintf ("done starting processor %d\n", c);
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}
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}
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